There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality and speed for multimedia applications and other applications. Newer technological processes have been designed to allow fast CMOS transistor operation. However, a resultant problem with integrated circuits having, for example, large numbers of transistors, is that the faster more and more CMOS transistors switch, the more likelihood of increased ground and power bounce or noise. The problem of ground and power bounce becomes increasingly difficult when millions of transistors are fabricated to operate at much higher speeds. The ground and power bounce can result, for example, from the switching current resultant from the switching of various circuits within an integrated circuit. In addition, it would be desirable to have a circuit and method that efficiently decelerated those circuits that do not require higher operational speeds.
One solution to decrease the effect of ground and power bounce has been not to use strong transistors if it is not critical for the chip performance. That means to use smaller width and longer length CMOS transistors for some circuits within an integrated circuit. For example, the slower circuits may use small width and longer length CMOS transistors to reduce the ground and power bounce. However, as the length of the CMOS transistor increases, it produces a larger input capacitor, parasitic capacitance. That means the previous stage has to be stronger to charge and discharge the next stage input capacitor. In addition, with smaller width devices, there is a technological size limit as to how small the width can be.
Consequently there exists a need for a circuit and method that can reduce the switching current resulting from higher speed transistors that is relatively simple and low cost in nature. A desired solution should not require increasing a length of a CMOS transistor nor decreasing the width of a CMOS transistor.